###############################################################################
#                                                                             #
#                Hardware Synthesis for EE180 MIPS (Lab 3)                    #
#                                                                             #
# This Makefile wraps the build processes that are involved in synthesizing a #
# hardware design for the Zedboard.                                           #
#                                                                             #
# Typical Usage:                                                              #
#   make             : Synthesize and generate the hardware bitstream file.   #
#   make clean       : Delete files which were generated by this Makefile.    #
#                                                                             #
# Requirements:                                                               #
#   - Xilinx tools                                                            #
#                                                                             #
# Author: Grant Ayers                                                         #
# Date:   February 2015                                                       #
#                                                                             #
###############################################################################


#---------- Basic settings ----------#
XILINX_SETTINGS      := /afs/ir.stanford.edu/class/ee/xilinx/14.7/ISE_DS/settings32.sh
LM_LICENSE_FILE      := 27000@cadlic0:5280@vlsi:5280@shimbala:5280@omnipotent:1717@cadlic0.stanford.edu:2100@ee-matlab.stanford.edu
BIT_FILE             := zed/implementation/system.bit
WRAP_FILE            := fpga.img
WRAP_SCRIPT          := bitToBin/convert_bitstream

#---------- No need to modify below ----------#
export LM_LICENSE_FILE

### Call helper functions ####

# Search for the first instance of a program in PATH
pathsearch = $(firstword $(wildcard $(addsuffix /$(1),$(subst :, ,$(PATH)))))

### Automatic settings and variables ####
SHELL  := $(call pathsearch,bash)

.PHONY: all clean setup bits wrap

all: wrap

wrap: $(WRAP_FILE)

$(WRAP_FILE): $(BIT_FILE)
	source $(XILINX_SETTINGS) && $(WRAP_SCRIPT) $(BIT_FILE) $(WRAP_FILE)
	@echo 'FPGA image ready.'

bits: $(BIT_FILE)

$(BIT_FILE): setup
	source $(XILINX_SETTINGS) && cd zed && $(MAKE) clean && $(MAKE) bits

setup:
	source $(XILINX_SETTINGS) && cd zed && xps -nw system.xmp <<< "exit"

clean:
	source $(XILINX_SETTINGS) && cd zed && $(MAKE) clean
	rm -f $(WRAP_FILE)
